1. Field of the Invention
The present invention relates to a bus arbitration communications scheme in a computer system having a multi-master system bus. More particularly, the present invention relates to at least one multistate microprocessor bus arbitration signal between a central processing unit (hereinafter referred to as a "CPU") and an external bus arbiter to indicate how urgent the CPU requires access to the bus.
2. Prior Art
It is commonly known that a multi-master bus is a communication structure connecting many devices such as processors, direct memory access devices (hereinafter referred to as "DMA devices") and other alternate bus masters, each of which are capable of accessing the bus and performing independent data transfers thereon. However, since the bus is a single resource which can transfer only one data element at a time, only one device at a time may have access to the bus. Such device is commonly referred to as a "bus master", which is selected usually by a bus arbiter being coupled to each of the devices through bus arbitration signals.
An example of conventional bus arbitration signals used to allocate control of a multi-master bus system is shown in FIG. 1, which illustrates a CPU 1, external main memory 2 and at least one alternate bus master 3, such as a DMA device, coupled together through a system bus 4. An external bus arbiter 5 is electronically coupled to the CPU 1 and the alternate bus master 3 in order to receive bus requests from the CPU 1 and the alternate bus master 3 and to grant such devices access to the system bus 4. Although FIG. 1 merely shows the external system bus 4 having at least two possible bus masters, namely the CPU 1 and the at least one alternate bus master 3, the system bus 4 is capable of supporting many different types of bus masters such as, for example, auxiliary processors.
The CPU 1 is coupled to the external bus arbiter 5 through three microprocessor bus arbitration signal lines; namely, a hold signal 8a, a hold acknowledge signal 8b and a bus request signal 8c referred to in this application as HOLD, HOLDA and BREQ respectively. The HOLD signal 8a is an input signal from the bus arbiter 5 into the CPU 1 indicating that one of the alternate bus masters 3 is attempting to access the system bus 4. The HOLDA signal 8b is an output signal from the CPU 1 into the bus arbiter 5 to acknowledge receipt of the HOLD signal 8a and to indicate that the CPU 1 does not currently require access to the bus 4. Finally, the BREQ signal 8c is a bus request signal outputted from the CPU 1 into the bus arbiter 5 which indicates that the CPU 1 requires access the system bus 4. Although not shown, similar arbitration signal lines would be implemented between any auxiliary processor coupled to both the external system bus 4 and the external bus arbiter 5.
With respect to the at least one alternate bus master 3, each of the alternate bus masters are coupled to the external bus arbiter 5 through two bus arbitration signal lines. For example, the first alternate bus master has a bus request ("REQ") 9a and a bus acknowledge ("ACK") 9b. The REQ signal 9a is inputted into the bus arbiter 5 from the first alternate bus master 3a in order to request access of the system bus 4 so that it can perform its services. The ACK signal 9b is outputted into the first alternate bus master 3a from the bus arbiter 5 to notify that it may begin accessing the bus 4 to transfer data thereon.
The above-mentioned conventional arbitration signal lines enable many devices to share a common system bus to perform independent data transfers. The operation of the above bus arbitration signals of the computer system shown in FIG. 1 as well as other bus arbitration signals further referenced in this application are simply considered to be "active high", although such signals may be implemented to be "active low".
Generally, an alternate bus master, such as the first alternate bus master 3a, requests control of the system bus 4 by first sending an active REQ signal 9a to the external bus arbiter 5. Upon receiving the active REQ signal 9a, the bus arbiter 5 sends an active HOLD input signal 8a to the CPU 1 to indicate that the first alternate bus master 3a is requesting control of the system bus 4. Thereafter, the HOLDA signal 8b is outputted from the CPU 1 to the bus arbiter 5 acknowledging that it has relinquished control of the system bus 4 to the first alternate bus master 3a and, as a result, the CPU 1 floats its address, data and control pins. Upon receipt of the HOLDA signal 8b, the bus arbiter 5 inputs the active ACK signal 9b into the first alternate bus master 3a indicating that it can access the system bus 4. If the CPU 1 needs to regain access to the system bus 4, it sends an active BREQ signal 8c to the external bus arbiter 5.
The CPU 1, as most high end processors used today, has an internal instruction/data cache 6 and an internal bus queue 7. An instruction/data cache 6 allows the CPU 1 to temporarily store instructions and data fetched from external main memory 2 to streamline instruction execution by reducing the number of instruction and data fetches required to execute a program. Therefore, the CPU 1 is capable of executing code without continually accessing the system bus 4.
A bus queue 7, on the other hand, enables the bus arbiter 5 to defer servicing a bus request from the CPU 1 if the CPU 1 can continue executing code instructions from the cache 6. However, this feature is not used to its full capability in a computer system using a conventional microprocessor bus arbitration communication scheme because the BREQ signal 8c indicates that the CPU 1 needs access to the system bus 4, but it does not provide sufficient information for the bus arbiter 5 to determine how urgently such access is needed (i.e., whether access can be granted after an alternate bus master finishes its data transfers).
As shown in FIG. 1, there does not currently exist any conventional multistate microprocessor bus arbitration signals which prioritize the urgency in which the CPU 1 requires access to the system bus 4. Thus, bus arbiters which control multi-master buses are commonly designed to grant access to the CPU 1 immediately after it receives the active BREQ signal 8c. As a result, the bus 4 is inefficient, especially in I/O intensive systems having many alternate bus masters because the CPU's request is more likely to disrupt another bus master's operations (e.g., the operations of the first alternate bus master 3a) even when the CPU 1 does not immediately require bus access. Furthermore, a computer system which requires alternate bus masters to immediately return access of the system bus 4 to the CPU 1 upon receipt of an active BREQ signal 8c is more likely to experience information loss resulting in a decrease in system performance.
Hence, it would be desirable to implement at least one multistate microprocessor bus arbitration signal to provide the bus arbiter with sufficient information to intelligently allocate access to the external system bus in order to increase its efficiency and performance.
Accordingly, it would be a great advantage and is therefore an object of the present invention to provide at least one multistate microprocessor bus arbitration signal to enable the external bus arbiter to determine how urgently the CPU requires access to the system bus.
Another object of the present invention is to provide a method and apparatus for increasing efficiency of a multi-master bus system.
A further object of the present invention is to provide a method and apparatus for increasing performance of a multi-master bus system.